Design and Performance Analysis of New Seventeen Level Reduced Switch Count Multilevel Inverter

Authors

  • Murugesan Manivel Karpagam Institute of Technology
  • Sivaranjani Subramani Sri Krishna College of Engineering and Technology
  • Lalitha Balasubramanian KPR Institute of Engineering and Technology
  • Bharani Prakash Thiagarajan KPR Institute of Engineering and Technology
  • Vijayalakshmi VJ Karpagam Institute of Technology
  • Lakshmanan Palani Rajagiri School of Engineering & Technology
  • Kesavan Tamilselvan Easwari Engineering College

DOI:

https://doi.org/10.4186/ej.2025.29.6.29

Keywords:

multilevel inverter, nearest level control, total harmonic distortion, pulse width modulation, cost function, total standing voltage

Abstract

Multilevel inverter has emerged newly as a very important alternate in the area of high-power medium-voltage energy control. The main problem in this technology is high devices, total standing voltage, cost, THD and efficiency. This paper's main goal is to provide a 17-level multilevel inverter with only 8 switches and 4 diodes. Four different unequal DC sources are used in this arrangement to produce the output voltage waveform with 17 levels. For the proposed inverter, the cost function per level, efficiency, total standing voltage, conduction losses, and switching losses have all been calculated in detail. Typical inverters have higher switching losses, prices, and harmonic distortion because they have more semiconductor power switches, diodes, capacitors, driver circuits, and DC sources. The switching components of the suggested arrangement have been controlled using the nearest-level control approach. The suggested multilevel inverter offers a higher efficiency of 98.24%, cost function of 5.7 for a weight coefficient of 1, improved power quality, and higher reliability. The total harmonic distortion produced by this inverter is 3.43%, which comes under the IEEE standard of 5%.

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Author Biographies

Murugesan Manivel
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Department of Electrical and Electronics Engineering, Karpagam Institute of Technology, Coimbatore, Tamil Nadu, India

Sivaranjani Subramani
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Department of Electrical and Electronics Engineering, Sri Krishna College of Engineering and Technology, Coimbatore, Tamil Nadu, India

Lalitha Balasubramanian
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Department of Electrical and Electronics Engineering, KPR Institute of Engineering and Technology, Coimbatore, Tamil Nadu, India

Bharani Prakash Thiagarajan
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Department of Electrical and Electronics Engineering, KPR Institute of Engineering and Technology, Coimbatore, Tamil Nadu, India

Vijayalakshmi VJ
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Department of Electrical and Electronics Engineering, Karpagam Institute of Technology, Coimbatore, Tamil Nadu, India

Lakshmanan Palani
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Department of Electrical and Electronics Engineering, Rajagiri School of Engineering & Technology, Kakkanad, Kerala, India

Kesavan Tamilselvan
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Department of Electrical and Electronics Engineering, Easwari Engineering College, Tamil Nadu, India

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Published In
Vol 29 No 6, Jun 30, 2025
How to Cite
[1]
M. Manivel, “Design and Performance Analysis of New Seventeen Level Reduced Switch Count Multilevel Inverter”, Eng. J., vol. 29, no. 6, pp. 29-41, Jun. 2025.
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